1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of forming a porous material layer in a semiconductor device.
A claim of priority is made to Korean Patent Application No. 2002-69262, filed on Nov. 8, 2002, the contents of which are incorporated herein by reference in their entirety.
2. Description of Related Art
As semiconductor devices become more highly integrated, the distances between adjacent interconnection lines have been reduced. Generally, an interlayer insulating layer occupies the region between the interconnection lines, and the dielectric constant (k) of the interlayer insulating layer creates a capacitive effect which delays the propagation of electrical signals applied to the interconnection lines. Accordingly, to improve the operating speed of the semiconductor device, it is desirable to form the interlayer insulating layer of a material having a low dielectric constant.
Silicon oxide has been typically employed as the material of the interlayer insulating layer. Unfortunately, however, silicon oxide has a dielectric constant of 3.9, which is generally too high to improve operating speeds in highly integrated devices.
One known method of reducing the dielectric constant of the interlayer insulating layer is to form the layer of a porous material. The pores or voids in the porous material decrease the dielectric constant of the layer as a whole. One drawback with the use of porous layers, however, is that the pores of the layer can cause over-etching when the porous layer is patterned, particularly when the layer contains carbon or carbon residues. For example, in the event that a porous material layer containing carbon residues is patterned to form via holes, the via holes may exhibit abnormal profiles.
In an effort to overcome the problem of over-etching, U.S. Pat. No. 6,451,712 to Dalton et al., entitled “Method For Forming A Porous Dielectric Material Layer In A Semiconductor Device And Device Formed”, describes a method of forming a low-k porous dielectric layer. The method of this patent is characterized in that a dense insulating layer is patterned using an etching technique, such as by reactive ion etching (RIE), prior to formation of pores in the dense insulating layer. Since the etching process precedes the formation of the pores in the dense insulating layer, over-etching that is otherwise caused by the pores can be prevented when patterning the insulating layer. However, the process of forming the via holes is typically performed using a photoresist pattern as an etching mask. Thus, the photoresist pattern must be removed using an ashing process after forming the via holes and prior to formation of the pores in the layer. Unfortunately, the ashing process can adversely increase deformation of the sidewall profiles of the via holes.